1. Field of the Invention
The present invention relates to a semiconductor memory device and a method of manufacturing the same. In particular, the present invention relates to an electrically programmable/erasable nonvolatile semiconductor memory device and a method of manufacturing the same.
2. Description of the Related Art
As one kind of an electrically programmable/erasable nonvolatile semiconductor memory device, a split-gate nonvolatile memory is publicly known (see, for example, Japanese Laid Open Patent Application JP-A-Heisei 9-92734). In the split-gate nonvolatile memory, only a part of a control gate overlaps with a floating gate. Moreover, not only the floating gate but also a part of the control gate is provided over a channel region, and hence not only the floating gate but also the part of the control gate is used for switching. For this reason, the split-gate nonvolatile memory has an advantage that an over-erasing is prevented.
A threshold voltage of a nonvolatile memory cell transistor varies depending on charge amount held in the floating gate. In a case of an N-channel memory cell transistor, for example, electrons are injected into the floating gate in a program operation, and thus the threshold voltage is increased. On the other hand, electrons are drawn out of the floating gate in an erase operation, and thus the threshold voltage is decreased. At the time of a read operation, a read current does not flow through a programmed cell but through an erased cell. It is therefore possible to sense data stored in the memory cell transistor by comparing the amount of the read current with a predetermined reference current Iref. As a reference transistor for generating the reference current Iref, a transistor having the same structure as the memory cell transistor has been conventionally used (see, for example, “Fujio Masuoka, Flash Memory Technology Handbook, Aug. 15, 1993, pp. 34-36). The reference transistor is fixed to an erased state.